Sample rate converters generally receive samples at a first rate, e.g., fband, up sample to a higher than desired rate, then down sample to the final rate, e.g. the input rate of a digital to analog converter. These devices employ a clock at the input rate to decrement the control word for a numerically controlled oscillator (NCO) to generate a new output sample each time the decremented NCO control word reaches zero or below i.e. underflows. Alternatively, the control word can be incremented and an output generated each time the NCO control word overflows. However, these approaches have shortcomings. There can be a frequency error when the desired conversion rate cannot be accurately represented with the available number of bits. There can be output timing jitter because the output samples can only be provided at the NCO clock rate.